{"id":557,"date":"2019-05-05T13:40:25","date_gmt":"2019-05-05T13:40:25","guid":{"rendered":"https:\/\/justanotherelectronicsblog.com\/?p=557"},"modified":"2019-05-05T13:40:27","modified_gmt":"2019-05-05T13:40:27","slug":"turning-a-cpu-into-a-soc","status":"publish","type":"post","link":"https:\/\/justanotherelectronicsblog.com\/?p=557","title":{"rendered":"Turning a CPU into a SoC"},"content":{"rendered":"\n

In my previous blog I wrote about a one page CPU in SpinalHDL. But just a CPU is a bit boring, time to turn it into a full System on Chip by adding memory, peripherals and even a UART bootloader. One of the great things of Spinal is the existing libraries, making adding some peripherals a lot less work compared to traditional hardware design languages.<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n\n\n\n\n

So, first things first, adding some instruction and data memory. Spinal supports generating memory with just a single line of code. So to generate 1Kword of RAM and 1K of instruction memory, the needed code is just this<\/p>\n\n\n\n

val RAM = Mem(Bits(8 bits),wordCount = 1024)\nval ROM = Mem(Bits(16 bits),wordCount = 1024)<\/pre>\n\n\n\n
Of course, reading and writing to memory is also required, luckily it’s fairly easy to do so as well. Loading a file in the ROM can easily be done, as the Hextools library support reading in an Intel hex file. The code to read and write from memory is straightforward as well, and some more info can be found the related Spinal website.<\/a><\/p>\n\n\n\n
\/\/default program\nHexTools.initRam(ROM, onChipRamHexFile, 0x0)\n\nRAM.write(\n\tenable  = areaCPU.CPU.io.we_ram,\n\taddress = areaCPU.CPU.io.addr_ram.asUInt,\n\tdata    = areaCPU.CPU.io.dout_ram\n)\n\nROM.write(\n\tenable  = progDataValid,\n\taddress = progCounter.resized,\n\tdata    = progData.asBits\n)\n\nval readValid = !areaCPU.CPU.io.we_ram\nCPU.io.din_ram := RAM.readSync(\n\tenable = readValid,\n\taddress = CPU.io.addr_ram.asUInt\n)\n\nCPU.io.din_instr := ROM.readSync(\n\taddress = CPU.io.addr_instr.asUInt.resized\n)<\/pre>\n\n\n\n
All peripherals are memory mapped, for now, all memory above address 896 is reserved for peripherals. The UART peripheral is made using the existing UART library <\/a>in Spinal and looks like this:<\/p>\n\n\n\n
val uart_readValid, uart_read, uart_writeValid, uart_write, uart_writeDone = Reg(Bits(8 bits)) init(\"00000000\")\nval uartCtrlConfig = UartCtrlGenerics(\n  dataWidthMax = 8,\n  clockDividerWidth = 16,\n  preSamplingSize = 1,\n  samplingSize = 5,\n  postSamplingSize = 2)\nval uartCtrl = new UartCtrl(uartCtrlConfig)\nuartCtrl.io.config.clockDivider := 156  \/\/12Mhz clock, 9600BAUD\nuartCtrl.io.config.frame.dataLength := 7  \/\/8 bits\nuartCtrl.io.config.frame.parity := UartParityType.NONE\nuartCtrl.io.config.frame.stop := UartStopType.ONE\n\nuartCtrl.io.write.valid := uart_writeValid.asBool\nuartCtrl.io.write.payload := uart_write\n\nuartCtrl.io.uart <> io.uart\n\nuart_readValid := uartCtrl.io.read.valid.asBits.resized\nuart_read := uartCtrl.io.read.payload\n\nio.din_ram := 0\n\nwhen(uartCtrl.io.write.ready){\n  uart_writeDone := 1\n}\n\nwhen(io.we_ram){\n  when(io.addr_ram === \"d907\"){\n    uart_writeDone := io.dout_ram\n  }.elsewhen(io.addr_ram === \"d908\"){\n    uart_write := io.dout_ram\n  }.elsewhen(io.addr_ram === \"d909\"){\n    uart_writeValid := io.dout_ram\n  }\n}.otherwise{          \n  when(io.addr_ram === \"d905\") {\n    io.din_ram := uart_readValid\n  }.elsewhen(io.addr_ram === \"d906\"){\n    io.din_ram := uart_read\n  }.elsewhen(io.addr_ram === \"d907\"){\n    io.din_ram := uart_writeDone\n  }<\/pre>\n\n\n\n
Most of it is setting up the UART library and decoding reads\/writes from memory to the UART registers. The other 2 peripherals, a Timer and GPIO are setup in a similar way. In the end, 2 pages of code, 132 lines, are needed for a GPIO, Timer and a UART peripheral, a lot more compact then a traditional HDL. The full code for the SoC can be found on my github<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"
In my previous blog I wrote about a one page CPU in SpinalHDL. But just a CPU is a bit boring, time to turn it into a full System on Chip by adding memory, peripherals and even a UART bootloader. One of the great things of Spinal is the existing libraries, making adding some peripherals […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[1],"tags":[],"class_list":["post-557","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"yoast_head":"\nTurning a CPU into a SoC - jaeblog<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/justanotherelectronicsblog.com\/?p=557\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Turning a CPU into a SoC - jaeblog\" \/>\n<meta property=\"og:description\" content=\"In my previous blog I wrote about a one page CPU in SpinalHDL. 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