Weird CPU architectures, the MOV only CPU

I like CPU architectures, especially weird, interesting and unusual ones. For example, the Intel iAPX 432 is still something I would love to play around with. Recently, I realized that a working CPU can be made with just a simple Move instruction. For this to work, everything needs to be memory mapped. The ALU, program counter, everything.

Of course, this idea is nothing new and this idea is called the Transport Triggered Architecture. I decided to have a look into this, how it works and make a simple TTA CPU.

How does a TTA CPU work

Before I can make a CPU, let’s look into what is so different in a TTA CPU. In most CPU’s, calculations are done using registers and some arithmetic logic unit. For example, to add 2 numbers, the assembly code could be:


In a TTA CPU, there is no ALU or registers in the CPU itself. Instead, they exist somewhere in memory. In order to add 2 numbers, they are moved from memory or registers, to the ALU. The ALU result is then moved back to memory/registers. Or in code:


In the simplest form, the CPU in a TTA CPU only needs to move data from one memory address to another. All calculations are done as a result of data being moved around. If you think, how would you jump to a different section of code, it’s easy. If the program counter is also in memory, a jump is as simple as moving a new address to the program counter.

A few TTA computers have been made, and even commercially sold. But in general, it’s a niche architecture that never has gotten popular. So let’s build one :D

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FPGA Softcore SoC shootout

Often it can be very handy to have a CPU in an FPGA. Though some are sold with an integrated CPU, most are not. A popular option is to use a so called Softcore CPU, a CPU that is implemented in the FPGA’s logic. I decided to have a look at a few popular and some less popular ones to see how easy they are to use, how fast they are and which might be a good choice for a project.

The contenders

I have a few requirements any CPU must meet:

1. There must be a GCC or LLVM compiler available
2. No vendor specific CPU, a CPU should run on all FPGA’s
If possible, a simple ready to go SoC with Uart, Timer and GPIO is nice, but no requirement.

Not that many requirements, so after some googling I found the following options:

  • VexRiscv
  • LEON3
  • PicoRV32
  • Neo430
  • ZPU
  • Microwatt
  • S1 Core
  • Swerv EH1

Sadly the S1 core and Swerv EH1 did not fit in my Arty board. I tried getting them small enough, but I need the Arty A7-100, so if anyone wants to sponsor me ;)

This still means 6 in total, and there are most likely some other good options as well that I missed.

From looking at the documentation, my gut feeling says that VexRiscv, LEON3 and Neo430 are going to be the nicest to use. I would say that the Microwatt, ZPU and the PicoRV32 are more hobby oriented. But let’s not get ahead of ourselves, each core will be looked at in more detail.

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Designing a custom FPGA board

In the last post I promised to talk about the custom hardware to drive the 64*64 LED matrix. I wanted custom hardware because my test setup looked a bit like this:

Hmm, spaghetti

This is not ideal of course, and I want to use my dev board for other things as well. Hence the need for a custom PCB. In this blog I’ll be going over the design of the custom FPGA board to replace the test setup.

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Driving a 64*64 RGB LED panel with an FPGA.

Browsing Ali-express is dangerous business. Before you know it you end up ordering strange things like a 64×64 pixel RGB LED matrix. These matrices (called HUB75 or HUB75E) are meant for use for the big outside LED displays.

There are several projects already involving these displays, but I wanted to do more FPGA stuff and this seems like a great excuse. A fast microcontroller can drive these displays. However, an FPGA is much better suited for this. The reason is that these displays do not have on board memory but need to be constantly refreshed to display an image. But when you get them up and running with an FPGA, the results are mighty fun

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Reverse engineering an old keyboard

Recently I got an old keyboard from the 1980s, it has a 20 pin ribbon cable connector, weights almost 3kg’s and has no information on Google. This should be fun.

The keyboard in question is a Computervision branded one, though the PCB says it’s an Amkey MPNK-68. Looking at the insides, the date codes on the circuit board are from 1984 and 1985, meaning this keyboard is probably from the end of the 1980s. Taking a look at the keycaps and all the special functions, it was most likely used for a terminal.

Now to reverse engineer it. A few tools are required to do so:

  1. A multimeter.
  2. A logic analyzer, like a Saleae Logic.
  3. Some screwdrivers to take the keyboard apart.
  4. A power suply, most likely 5V

Very simply put, the steps are as follows:

  1. Open the keyboard
  2. See what the pinout of the connector is.
  3. Power the keyboard.
  4. Hook up a logic analyzer to all signal pins.
  5. Figure out how it works, is it a serial protocol, parallel, something else.
  6. Build a converter using a microcontroller board like an Arduino.
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A look inside a Marconi signal generator

Recently I got a Marconi Instruments 2019 signal generator, capable of generating signals from 80Khz up to 1040Mhz. It can also modulate these signals with AM, FM and more. This instrument is from the mid 80s and is, as far as I can test, still in good operational order.

A signal generator capable of generating over 1Ghz is pretty impressive, especially in the 80s, so let’s have a look inside this unit and see how it’s made. I have very little RF knowledge, for a good explanation on how this thing works I would recommend the service manual. It can be found with some google magic and contains 240 pages filled with explanation of this signal generator.

Warning: This page contains a lot of big images.

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Turning a CPU into a SoC

In my previous blog I wrote about a one page CPU in SpinalHDL. But just a CPU is a bit boring, time to turn it into a full System on Chip by adding memory, peripherals and even a UART bootloader. One of the great things of Spinal is the existing libraries, making adding some peripherals a lot less work compared to traditional hardware design languages.

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A one page CPU in SpinalHDL

FPGA’s are fun and interesting devices, sadly the usual ways of programming them, Verilog and VHDL, are tedious and annoying to work with. Sadly most FPGA tools support only these languages. Luckily a few projects exist to make a nicer and more fun language to work with, which are translated to either Verilog or VHDL so they can be used with all normal FPGA tools. One of these languages is SpinalHDL, a Scala based language that promises more abstraction, less boilerplate code and also has a good amount of already existing libraries. The only downside is the long name, SpinalHDL, so I’ll short it to Spinal for now :

To try out and learn Spinal a bit, I decided to make a CPU, an always popular project for FPGA’s. To make it a bit more interesting, I wanted to make a CPU which code fits on a single page of paper, inspired by the fun CPU’s made by Revaldinho, which can be found here. Those CPU’s also have the added rule of having a emulator and assembler also fit in a single page of paper, which I choose not to stick to.

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Getting an IBM AS/400 Midrange computer on the internet

Recently I’ve gotten a hold of an old IBM mid-range computer, an AS/400 150.
This is an 1997 server very much aimed at businesses, pay-rolling, inventory management and such. It can be used as a multi user system, with users logging in via a terminal.
The operating system it runs is OS/400 and that is also the only OS it can run, no Linux available for this system.
Of course it comes with all the fun programming languages like COBOL and RPG, all the business classics :)
It’s compatible with the IBM system/36, so any programs made for an 80’s S/36 machine run without problems on the AS/400 machines. It also looks very much 90s, though I personally like the cover at the back, hiding all ports.

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Hello World on the Lichee Tang RISC-V/FPGA board

A Chinese company recently launched a small dev board with some interesting features, it’s one of the very few boards with a RISC-V CPU, like the SiFive HiFive1, at least, I though. Unlike the HiFive1 board, the Lichee Tang doesn’t use a custom RISC-V microcontroller, instead it has a FPGA IC with a RISC-V core pre-loaded. This also means it’s possible to use it as an FPGA board, add custom things in the FPGA next to the CPU and so on. And this is just where the interesting tidbits start. Sadly, the documentation currently is mostly in Chinese. So let’s change that and make a hello world project. Meaning, get a toolchain up and running, recompile the FPGA project and load it all on the dev board. Don’t worry, I also created a virtual machine with all the work done already.

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